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RiscCPU8
- 可综合的VerilogHDL设计实例: ---简化的RISC 8位CPU设计简介---
RiscCpu
- 4位RISC指令CPU源码,需要的朋友可以看看!
S3C44B0X中文技术文档
- 介 绍 三星的S3C44B0X 16/32位RISC处理器被设计来为手持设备等提供一个低成本高性能的方案。 S3C44B0X提供以下配置：2.5V ARM7TDMI 内核带有8Kcache ;可选的internal SRAM;LCD Controller(最大支持256色STN，使用LCD专用DMA)；2-ch UART with handshake(IrDA1.0, 16-byte FIFO) / 1-ch SIO； 2-ch gener
mips_project
- 我用verilog写的risc指令集的mips的cpu。可以支持定点运算。顶层单元是top。-I used to write verilog mips risc instruction set of the cpu. To support fixed-point arithmetic. Top-level unit is the top.
cputest.rar
- 自己刚写的一个RISC的cpu，位宽16，主要是测试其中的逻辑，数据宽度是一位，可以很容易扩展,Writing just one of their own RISC the cpu, bit 16, are testing one of the main logic, data width, a, can be easily extended
Pccard
- pccard driver s3c2440.The S3C2440A offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB
Arca2Core
- Arca2的规格文档，一种RISC结构CPU。-Arca2 specification documents, a RISC structure of CPU.
W90P710CD_CDGf
- The W90P710 is built around an outstanding CPU core, the 16/32 ARM7TDMI Risc processor
cpudesheji
- CPUname是RISC处理器，采用普林斯顿体系结构，CPU与数据存储器间的通信使用Load/Store指令实现，数据存储采取统一的32位字长格式，32位定长指令，地址指令格式。使用专用数据通路结构，四级流水线，分为取指及译码，取数，运算，回写四步，拥有相关专用通路以解决数据相关问题,对跳转指令应用分支预测技术，使其不影响流水。-CPUname is a RISC processor, using the Princeton architecture, CPU and data memory,
1
- HCS12X微控制器系列是HCS12系列的升级版，XGate外围处理器又是其重要的组成原件。XGATE是一款能够独立运行在主CPU上的可编程内核，可以匹配所有S12终端以及RISC设备。本篇应用比价就介绍了如何配置以及使用XGATE。-HCS12X micro-controller family is the HCS12 series of upgrades, XGate external processor is also an important component of its origi
mips
- cpu---risc---mips源代码-cpu---risc---mips
ourdev_441156
- AVR单片机是1997年由ATMEL公司研发出的增强型内置Flash的RISC(Reduced Instruction Set CPU) 精简指令集高速8位单片机。AVR的单片机可以广泛应用于计算机外部设备、工业实时控制、仪器仪表、通讯设备、家用电器等各个领域。-AVR Microcontroller ATMEL Corporation in 1997 developed by the enhanced built-in Flash of the RISC (Reduced Instructio
cpu16
- 16位cpu设计vhdl源码。主要实现risc机器模型-16-bit cpu design code
Verilog-HDLTOP-DOWN
- 用Verilog HDL的建模来设计一个经简化的只有八条指令、字长为一字节的RISC中央处理单元（CPU）的顶层设计。-Modeling with the Verilog HDL to design a simplified and only eight instructions, word length is a byte RISC central processing unit (CPU) of the top-level design.
sparc_verilog
- open risc微处理器的verilog源码。基于sparc架构，可以直接综合。适合cpu的学习-open risc microprocessor verilog source. Based on sparc architecture can be directly integrated. Learning for the cpu
simplesim-3v0e
- SimpleScalar 模拟器模拟的是一个超标量，5级流水的RISC体系结构的CPU模型，提供了从最简单到超标量乱序发射的不同的模拟程序。sim-outorder 是一个具有完整功能的模拟程序。在sim-outorder中使用了几乎所有的模拟资源，在阅读代码之前对模拟的体系结构和模拟资源充分的了解，能够大大提高下一步工作的效率。-SimpleScalar tool
smdk2413_application_note_rev10
- SMDK2413 (Samsung MCU Development Kit) for S3C2413X is a platform that is suitable for code development of SAMSUNG s S3C2413X 16/32-bit RISC microcontroller (ARM926EJ-S) for hand-held devices and general applications. The S3C2413X consists of 16-/32-
VHDL-for-Datapath
- MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - reg
Code-Vision-AVR-C-11
- AVR 单片机的C语言例程 一共有30多个，基本通用-AVR RISC(Reduced Instruction Set CPU
arm-gcc-3.4.4-gm8180.tar.bz2
- GM’s GM8180 MDC1 hardware environment is a highly efficient RISC-based platform for the purpose of verifying and evaluating AMBA-based designs in the early development stage. The complete set of MDC1 GM8180 platform consists of a main board (MB12